Paging is a memory-management that allows the physical location (known as physical address space) of a process to be non-contiguous. Paging avoids external fragmentation and the need for condensation. It additionally takes care of the wider issue of shifting size fitting memory chunks at backing stores; most memory management schemes experienced the issue with the plan used prior to the introduction of the paging. This issue emerges in light of the fact that, when some code fragments or data residing in the main memory must be interchanged, space must be found at the backing store.

In other words, paging can be defined from the following point;

  • Paging is a storage mechanism used to retrieve processes from secondary memory storage units as pages in the main memory storage unit.
  • The actual inkling behind paging is to segment each process into small fixed-sized chunks called pages similarly the main memory will also be divided into equal-fixed size chunks called frames.
  • A page of the process is to be stored in any one frame of the main memory. Pages can be stored at different locations of main memory but the priority is always to find contiguous frames.

Process pages are brought into the main memory only when they are needed otherwise they remain in secondary memory storage.

The different operating systems define different frame sizes. The size of each frame should be equal. The page size should be the same as the frame size, taking into account the fact that the frame is mapped in paging.

Hardware Support Block diagram for Paging in Operating System
Hardware Support Block diagram for Paging in Operating System

Figure 1: Hardware Support Block diagram for Paging in Operating System

Hardware support for paging appears in Figure 1. Each address generated by the CPU is partitioned into two sections:

  1. A page number (p): The page number is utilized in the page table as an index. The page table contains the base address of each page in physical memory.
  2. A page offset (d): This base address is joined with a page offset to characterize the physical memory address that is sent to the memory unit.

The hardware is characterized by page size (like the size of the frame). Page size is typically a power of 2, fluctuating between 512 bytes and 16 MB for each page, depending on system architecture. Selecting the power of 2 as a page size makes the interpretation of a page number and a logical address in the page offset particularly simple. On the off chance that the size of the logical address space is 2m and the size of the page is 2n which is addressing units (bytes or words), the high-order m-n bits of logical address at that time assign the page number and n Low-order bits provide page offset. Therefore, the valid logical address is as follows:

Paging3-minwhere p is an index into the page table and d is the displacement within the page.

Paging model of logical and physical memory
Paging model of logical and physical memory

Figure: Paging model of logical and physical memory

Example

Let us consider the main memory size 16 Kb and the frame size 1 Kb, so the main memory will be divided into a collection of 16 frames of 1 Kb each. There are 4 processes in the systems which are P1, P2, P3 and P4 of each 4Kb. Each process is divided into 1 Kb page so that one page can be stored in one frame. Initially, all frames are empty so pages of processes will be stored in a contiguous way. The frames, the page and the mapping between the two are shown in the image below.

Addressing of pages in logical and main memory
Addressing of pages in logical and main memory

Figure: Addressing of pages in logical and main memory

Relation of page number and offset with logical address and physical address
Relation of page number and offset with logical address and physical address

Figure: Relation of page number and offset with logical address and physical address

Solved examples to calculate logical address through logical address space and vice-versa;

Example1:

  • If Logical Address = 31 bit, then Logical Address Space = 231 words

i.e. 2Gb words (where; 1Gb = 230)

  • If Logical Address Space = 128 M words = 27 * 220 words,

then Logical Address = log2 227 = 27 bits

  • If Logical Address Space = 128 M words = 27 * 230 words,

then the logical address = log2237 = 37 bits

Solved examples to calculate physical address through physical address space and vice-versa;

  • If Physical Address = 22 bit,

then physical address space = 222 words = 4 M words (1 M = 220)

  • If Physical Address Space = 16 M words = 24 * 220 words

then Physical Address = log2 224 = 24 bits

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